The present invention relates to semiconductor devices and methods of forming the same, and more particularly, to memory devices and methods of forming the same.
A nonvolatile memory device typically includes a peripheral circuit for performing program, erase and read operations on memory cells. The peripheral circuit generally includes a high-voltage device for applying a high voltage to the cell and a low-voltage device for applying a low voltage to the cell. The peripheral circuit also typically includes a resistor for adjusting signal delay, voltage and/or current levels. Meanwhile, a cell gate electrode and a peripheral circuit gate electrode of the memory device typically need a metal-containing layer for enhancing the operating speed of the device. In order to enhance the read/write speed of the memory cell, an electron flow from the gate electrode may be blocked by forming an electrode on a gate insulation layer of the memory cell using a conductive material with a work function of 4.0 eV or more as described, for example, in Korean Patent Application No. 2003-0075516. In general, a conductive material of a high work function is preferably a metal-containing layer. However, the metal-containing layer generally has a very-low sheet resistance and is, thus, often unsuitable for a resistor as a resistor formed using a metal-containing layer with a very-low sheet resistance generally must have its area increased so as to obtain a desired resistance. This may cause difficulties in providing a high integration of the memory device.
In general, the cell gate electrode, the peripheral circuit electrode and the resistor are formed in the same level. Accordingly, when the gate electrode is formed to include a metal-containing layer, the metal-containing layer is generally also formed in the resistor region. Therefore, an additional photolithography process and an etch mask are typically required to remove the metal-containing layer from the resistor region. In addition, while a cell gate pattern generally needs a charge trapping layer or a floating gate capable of storing an electric charge, the peripheral circuit gate electrode generally needs a gate insulation layer. When a peripheral circuit gate pattern has a floating gate or a charge trapping layer, the memory cell may be unnecessarily programmed by application of a high voltage thereto, causing an increase in a threshold voltage. The peripheral circuit gate pattern typically should not have a floating gate or a charge trapping layer in order to reduce the operating voltage of a peripheral circuit transistor. Thus, when a charge trapping layer is formed in a cell array region, an additional photolithography process and an etch mask are generally used to remove the charge trapping layer from a peripheral circuit region. As such, a very complicated method is generally used to form a nonvolatile memory device having cell gate electrodes, peripheral circuit electrodes and resistors.